LSI construction of complex circuit design provides a compact solution to circuit problems by the high packing density available in this art. This is in large part attributable to the very high percentage of the total volume consumed in the interconnecting wiring and connecting plugs required in older and more conventional designs utilizing external wiring between standard element chip packages. Since an extremely great number of circuit components must be contained on one substrate in the LSI circuit, the manufacturing process is much more complex than with a conventional circuit. As a result, the custom approach to a maximum utility of the area of the substrate by individually designing the component location and metallization connection for each required circuit is much more difficult in the LSI field than in smaller ICs.
In order to remove this deficiency present in the custom approach, a masterslice concept was developed for bipolar devices. With the masterslice concept or approach all wafers can be processed exactly alike up to the personalizable levels, and then stockpiled. Since personalization requires only a few process steps, this provides a significant reduction in the turnaround time. The masterslice concept also lends itself to auto-place and auto-wire programs which reduce the design cycle for a particular chip. Other advantages include array-like yields and lower cost for releasing each individual circuit design.
One customizing approach is described in U.S. Pat. No. 3,983,619, in which an LSI chip is made of an array of unit cells. All of the unit cells on the chip perform the same logical function, that is, AND, NAND, or OR. The unit cells are simple depletion-load circuits. No provision is made for powering up, that is, for having more than one power level in the unit cell. Another approach is described in U.S. Pat. No. 4,141,662, in which an LSI chip contains a fixed number of different logic functions. There are 72 NAND logic cells and 32 D flip-flop cells on the chip. No provision is made for powering up the logic cell.
Another approach is described in the IBM Technical Disclosure Bulletin Vol. 22, No. 5, October 1979, page 2018 to 2020 which utilizes a master image. Each part number generated using this technique has a unique set of masks; no processing of a wafer can be started until the unique set of masks for the given part number is submitted to the processing group. That is, the master-image concept only specifies where individual cells can be placed, and does not specify any FETs or other contents of the cells. With this technique, none of the wafer processing can be completed prior to the submission of a release for each individual circuit design.
One master-slice approach that has been utilized with FET devices is described in the IBM Technical Disclosure Bulletin Vol. 22, No. 2, July 1979, page 447. A flexible FET logic cell is personalized at the contact level and at the first metal level. This allows for six logical functions. This technique uses a single depletion load circuit and does not offer any provision for powering up the logic cell. Moreover, this design requires extra processing steps, since contact vias already formed must be later specifically opened during personalization.